Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications

Most mobile and wearable devices present digital audio signal processing capabilities. Since the nature of signals is analog, there a need to use analog-to-digital converters (ADCs) with high-resolution for high signal-to-noise ratio acquisition. This paper presents high-level modeling design continuous-time third-order sigma-delta modulator (CT-SDM) an FIR DAC devices, using supply voltage 0.5 V. The divided in three steps carried out Delta-sigma toolbox discrete-time (DT-CT) transformation. First, schematic implementation verilogA models done estimate first-integrator amplifier specifications provide 14 bits ENOB. Following, two-stage inverter-based designed used verify strategy. Finally, transistor-level OTAs comparator evaluate CT-SDM performance. An in-depth analysis discussion are presented explain achieved results those circuits.